In a typical flip-chip electronic package, an integrated circuit (IC) chip (also referred to as a die) is joined to a substrate through a series of solder connections. The substrate is typically a ceramic or organic laminate, and the solder connections may comprise controlled collapse chip connection (C4) bumps. An underfill material is provided in the space between the chip and the substrate and encapsulating the solder connections. The underfill is usually an epoxy resin and commonly includes inorganic fillers such as silica.
A common problem with flip-chip packages is delamination of various layers of the package. For example, delamination of the underfill from the chip can result from mismatched coefficients of thermal expansion (CTE) between the respective materials of the package. When the package is raised to an elevated temperature, e.g., during thermal cycling testing or field operation (actual use), the mismatched CTE's can produce thermally-induced mechanical stress within the package, which can lead to delaminating, cracking, and electronic failure of the chip.
In light of the delaminating, and for development and manufacturing troubleshooting purposes, it is desirable to have a method to rapidly predict the adhesion reliability of the underfill to the chip in thermal cycling testing or field operation. Some adhesion tests are performed using underfill material adhered to a surface similar to that used in a package. However, these tests do not utilize an actually manufactured IC module, and thus do not accurately measure the adhesion of the underfill as it is affected by aspects of the manufacturing processes. As a result, these tests do not show good correlation with the actual reliability of the packages, due to differences with the geometry and process conditions between the manufactured modules and laboratory experiments. Other adhesion tests do utilize a manufactured module, but are performed at a macroscopic scale, e.g., shearing an entire chip off of the laminate. Such macroscopic tests do not isolate the adhesion of the underfill, and instead measure the adhesion of the entire interface between the chip and laminate including the adhesion at the solder connections.
Accordingly, there exists a need in the art to overcome the deficiencies and limitations described hereinabove.